High-speed Instruction-set Coprocessor for Lattice-based Key Encapsulation Mechanism: Saber in Hardware. IACR Transactions on Cryptographic Hardware and Embedded Systems, [S. l.], v. 2020, n. 4, p. 443–466, 2020. DOI: 10.13154/tches.v2020.i4.443-466. Disponível em: https://ojs.ub.ruhr-uni-bochum.de/index.php/TCHES/article/view/8690.. Acesso em: 27 nov. 2024.