High-speed Instruction-set Coprocessor for Lattice-based Key Encapsulation Mechanism: Saber in Hardware. TCHES [Internet]. 2020 Aug. 26 [cited 2024 Nov. 27];2020(4):443-66. Available from: https://ojs.ub.ruhr-uni-bochum.de/index.php/TCHES/article/view/8690